In a 2.5D package, multiple IC chips (e.g., a logic chip, a memory stack, etc.) are mounted close together to improve performance, bandwidth and/or functionality. Since multiple IC chips are close to each other, they are thermally coupled together. If one of the IC chips dissipates more power than the others, heat may flow from the high power IC chip to a lower power IC chip. The IC fabrication technology for each IC could be different, and hence the junction temperature specification can be different as well depending on technology, functionality, performance and bandwidth. The lower power IC could have a lower junction temperature specification. As a result, thermal management of heat generated in the 2.5D package becomes challenging.
For example, FIG. 1 illustrates heat flow in a package due to thermal interaction between IC chips. In FIG. 1, a substrate 101, with an upper surface and a lower surface, has solder balls 103 metallurgically bonded to a solder ball receiving area on the lower surface of the substrate 101. IC chips (e.g., a logic chip 105 and a memory stack 107) are attached to the upper surface of the substrate 101 by controlled collapse chip connection (C4) balls 109 via an interposer 108. The logic chip 105 and the memory stack 107 are mounted on the interposer 108 with micro-bumps 106. A lid 111 is formed over the logic chip 105 and the memory stack 107. The lid 111 is thermally connected to the logic chip 105 and the memory stack 107 by a thermal interface material (TIM1) 113. The lid 111 also includes lid feet in mechanical contact with the perimeter of the upper surface of the substrate by an adhesive 115. A heat sink 117 is formed over the lid 111. The heat sink 117 is thermally connected to the lid 111 by TIM2 119. Arrows 121 represent heat flow through the package. As illustrated, though the heat sink 117 includes a plurality of fins, heat generated within the package continues to flow between the logic chip 105 and the memory stack 107. As a result, the semiconductor devices tend to overheat or fail because of insufficient heat transfer.
A need therefore exists for methodology enabling formation of a semiconductor packaged with reduced thermal interaction between the IC chips and the resulting device.